This might be on the edge of applicability for qick-specific issues, but I thought I'd ask just the same. I've both a ZCU216 and ZCU208 in my lab, both with CLK204 and XM655 adapters (both ZCU's are cabled to the CLK104 module the same, and the SMAs on the XM655 are connected the same) The intent is to run qick on the ZCU208 because of our requirements. I've taken the ZCU216 Vivado model and adapted it to the ZCU208 (it was mostly an issue of reducing the number of DACs and adding axis terminators to the tproc and switch IPs where needed). The issue is the DAC clocks aren't being detected as locked. I see the following output from debug that I added in qick.py for both ZCU's:

ZCU216 list_rf_blocks: configuring DACs and ADCs to list Adding DAC 2 DAC 2 - 0 slice enabled DAC 2 - 1 slice enabled DAC 2 - 2 slice enabled DAC 2 - 3 slice enabled Adding DAC 3 DAC 3 - 0 slice enabled DAC 3 - 1 slice enabled DAC 3 - 2 slice enabled Adding ADC 2 ADC 2 - 0 slice enabled ADC 2 - 2 slice enabled clocks_locked: dac_tiles= [2, 3] adc_tiles= [2] iTile DAC: 2 PLLLockStatus= 1 iTile DAC: 3 PLLLockStatus= 1 iTile ADC: 2 PLLLockStatus= 1 dac_locked: [False, False] adc_locked: [False] set_all_clks: board= ZCU216 resetting clocks: 245.76 491.52 lmk: [{'spi_device': PosixPath('/dev/spidev1.1'), 'compatible': 'lmk04828', 'num_bytes': 3}] lmx: [{'spi_device': PosixPath('/dev/spidev1.3'), 'compatible': 'lmx2594'}, {'spi_device': PosixPath('/dev/spidev1.2'), 'compatible': 'lmx2594'}] clocks_locked: dac_tiles= [2, 3] adc_tiles= [2] iTile DAC: 2 PLLLockStatus= 2 iTile DAC: 3 PLLLockStatus= 2 iTile ADC: 2 PLLLockStatus= 2 dac_locked: [True, True] adc_locked: [True]

Note with the ZCU216 that the first call to clocks_locked shows both DACs and the ADC clock as not locked, and the second call to clocks_locks shows both DACs an the ADC clocks as locked (is the PLLLockStatus value from one of the status registers on the LMX2594?).

ZCU208 list_rf_blocks: configuring DACs and ADCs to list Adding DAC 2 DAC 2 - 0 slice enabled DAC 2 - 2 slice enabled Adding DAC 3 DAC 3 - 0 slice enabled DAC 3 - 2 slice enabled Adding ADC 2 ADC 2 - 0 slice enabled ADC 2 - 1 slice enabled clocks_locked: dac_tiles= [2, 3] adc_tiles= [2] iTile DAC: 2 PLLLockStatus= 1 iTile DAC: 3 PLLLockStatus= 1 iTile ADC: 2 PLLLockStatus= 2 dac_locked: [False, False] adc_locked: [True] set_all_clks: board= ZCU208 resetting clocks: 245.76 491.52 lmk: [{'spi_device': PosixPath('/dev/spidev1.1'), 'compatible': 'lmk04828', 'num_bytes': 3}] lmx: [{'spi_device': PosixPath('/dev/spidev1.3'), 'compatible': 'lmx2594'}, {'spi_device': PosixPath('/dev/spidev1.2'), 'compatible': 'lmx2594'}] clocks_locked: dac_tiles= [2, 3] adc_tiles= [2] iTile DAC: 2 PLLLockStatus= 1 iTile DAC: 3 PLLLockStatus= 1 iTile ADC: 2 PLLLockStatus= 2 dac_locked: [False, False] adc_locked: [True]

Note with the ZCU208 that the first call to clocks_locked shows both DAC clocks as not locked but the ADC as locked (this is odd), and the second call to clocks_locks shows both DACs still not locked but the ADC clock as locked. So the locked status doesn't change after the clocks are programmed (I do see the ZCU108 CLK104 PLL locked LEDs flash when the clocks are reset). Is there anything in the PetaLinux build that would cause this? I can run xrfclk.py and the Xilinx embeddedsw gitlab version, xrfclk.c, on both the ZCU216 and the ZCU208, and the CLK104 board PLL locked LEDs flash off, then on in both cases (for both the xrfclk.c built for Linux and the Python version). Can anyone think of something I've missed in the port that would cause this? Thank you!

Has there been any consideration given to making the tproc64x32 IP have a configurable number of output channels instead of fixed at eight, so that the number can be set in Vivado? The reason I ask is, that it appears as though it would be simpler to reduce the number of output channels on the tproc IP with my ZCU208 port than add more DACs with two more clock domains to make up the difference between the ZCU216 and ZCU208 DAC configuration.

When running the demo program “02_Sweeping_variables”, I try to change some parameters in the config dict (longer relax_delay, more reps and expts), I found some points in the middle got wrong data.

The config dict I used is: config={"res_ch":7, # --Fixed "relax_delay":5000, # --Fixed "res_phase":0, # --Fixed "pulse_style": "const", # --Fixed "length":100, # [Clock ticks] "readout_length":200, # [Clock ticks] "pulse_gain":0, # [DAC units] "pulse_freq": 100, # [MHz] "adc_trig_offset": 100, # [Clock ticks] "reps":60, # New variables "expts": 40, "start":0, # [DAC units] "step":50# [DAC units] }

And the result looks like:

If I change the relax_delay to 0, the result looks normal.

I try to debug this by looking into the acquire_round function of RAveragerProgram, and I think the problem is probably because the count register (which is accessed via tproc.tproc.single_read(addr=1) ) is counting ahead of the experiment runs.

Here I added the following print lines around line 424 of qick.averager_program to keep track of this count register.

And I got outputs like:

It seems that whenever the tProcessor starts, this count register will directly jump to 8. For example in the result above, the relax_delay is 5ms, but the counter jump to 8 in 3.5e-5s. (Iterations after this seem to be fine, it will count to 9, 10, 11 after each relax_delay …… )

I think this problem didn't show up for short relax_delay because the time python took to run from reading the counter to acquiring the data is long enough for the board to finish 8 more runs, so we didn't took data that doesn't exist yet. But for long relax_delay , when the counter count to 100, we actually only have 92 data in the buffer.

The assembly "set" command takes in a bunch of registers for controlling various pulse parameters specific to the DAC (freq, phase, gain, etc.). The documentation shows: set ch, p, $ra, $rb, $rc, $rd, $re, $rt:

This makes it quite annoying to use the set instruction for ADC / digital marker triggering. E.g. if I want to trigger an ADC readout or digital marker at a time defined in a register (so seti won't do), I need to configure $ra, $rb, $rc, $rd, $re, $rt instead of just $rt and a single register containing all of the marker/trigger bits.

I think it would be nice to have a separate instruction for this purpose e.g. set2 ch, p, $ra, $rt where $ra contains all of the marker/trigger bits.

Hi I am getting a weird bug when I do start up qick via a client Input (connecting to nameserver and printing out qick soc object):

import Pyro4 from qick import * from qick import QickConfig Pyro4.config.SERIALIZER = "pickle" Pyro4.config.PICKLE_PROTOCOL_VERSION=4

ns_host = '192.168.0.133' #ip of client pc where the nameserver is running ns_port = 8000 server_name = "myqick"

ns = Pyro4.locateNS(host=ns_host, port=ns_port)

soc = Pyro4.Proxy(ns.lookup(server_name)) soccfg = QickConfig(soc.get_cfg()) print(soccfg)

Output:

KeyError Traceback (most recent call last) Cell In [8], line 3 1 soc = Pyro4.Proxy(ns.lookup(server_name)) 2 soccfg = QickConfig(soc.get_cfg()) ----> 3 print(soccfg) File c:\users\chakram_meas\documents\github\qick\qick_lib\qick\qick_asm.py:48, in QickConfig.str(self) 47 def str(self): ---> 48 return self.description() File c:\users\chakram_meas\documents\github\qick\qick_lib\qick\qick_asm.py:88, in QickConfig.description(self) 86 lines.append("\n\t%d readout channels:" % (len(self['readouts']))) 87 for iReadout, readout in enumerate(self['readouts']): ---> 88 if readout['tproc_ctrl'] is None: 89 lines.append("\t%d:\t%s - controlled by PYNQ" % (iReadout, readout['ro_type'])) 90 else: KeyError: 'tproc_ctrl'

This error does not occur when I run qick directly from xilinx board (instead of client/external pc)

I am trying to characterize a qubit using the notebook for the qubit demo. The demo suggests doing the readout with a mixer and LO (on a ZCU111) but considering that the RFSoc4x2 board has a sampling frequency of 10Gsps I am trying to do it without mixer. But I am not getting any nice results.

Is it possible to do readouts on this board without mixers? or should I use mixer and LO?

When I try to print out the following: soc = Pyro4.Proxy(ns.lookup(server_name)) soccfg = QickConfig(soc.get_cfg()) print(soccfg)

The print line produces the following error:

`KeyError Traceback (most recent call last) in 1 soc = Pyro4.Proxy(ns.lookup(server_name)) 2 soccfg = QickConfig(soc.get_cfg()) ----> 3 print(soccfg)

c:_lib\python\qick\qick_lib\qick\qick_asm.py in str(self) 31 32 def str(self): ---> 33 return self.description() 34 35 def getitem(self, key):

c:_lib\python\qick\qick_lib\qick\qick_asm.py in description(self) 76 readout['avg_maxlen'], readout['buf_maxlen'], readout['trigger_bit'], readout['tproc_ch'])) 77 ---> 78 lines.append("\n\t%d DACs:" % (len(self['dacs']))) 79 for dac in self['dacs']: 80 tile, block = [int(c) for c in dac]

c:_lib\python\qick\qick_lib\qick\qick_asm.py in getitem(self, key) 34 35 def getitem(self, key): ---> 36 return self._cfg[key] 37 38 def setitem(self, key, val):

KeyError: 'dacs'`

Indeed when I print out the configuration using soccfg.get_cfg() I get the the output below which does not contain 'dacs'

{'board': 'ZCU216', 'refclk_freq': 245.76, 'fs_proc': 430.08, 'gens': [{'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 0, 'tproc_ch': 1, 'dac': '20', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 1, 'tproc_ch': 2, 'dac': '21', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 2, 'tproc_ch': 3, 'dac': '22', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 3, 'tproc_ch': 4, 'dac': '23', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 4, 'tproc_ch': 5, 'dac': '30', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 5, 'tproc_ch': 6, 'dac': '31', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}, {'type': 'axis_signal_gen_v4', 'maxlen': 65536, 'b_dds': 32, 'switch_ch': 6, 'tproc_ch': 7, 'dac': '32', 'fs': 6881.280000000001, 'f_fabric': 430.08, 'samps_per_clk': 16, 'maxv': 32766, 'maxv_scale': 1.0}], 'readouts': [{'avg_maxlen': 16384, 'buf_maxlen': 1024, 'b_dds': 32, 'adc': '20', 'fs': 2457.6, 'f_fabric': 307.2, 'trigger_bit': 14, 'tproc_ch': 0}, {'avg_maxlen': 16384, 'buf_maxlen': 1024, 'b_dds': 32, 'adc': '22', 'fs': 2457.6, 'f_fabric': 307.2, 'trigger_bit': 15, 'tproc_ch': 1}], 'iqs': [], 'tprocs': [{'trig_output': 0, 'pmem_size': 8192.0, 'dmem_size': 4096}]}

Greetings from UC Berkeley.

Thanks for the phenomenal work! I have followed the tutorials and got myself familiar with qick library.

I am now planning to perform frequency conversion with an external LO and I have purchased LMX2595 evaluation board for this purpose. It is similar to the one used in the RFboard front end. I would like to be able to control it via SPI through Qick. I have followed the schematic and connected the SPI wires accordingly. However the SPI IPs are missing and I can't Initialize the board using RFQickSoc(). Any suggestion on how to load them and set the LO frequency to a particular frequency?

Thanks, Mutasem

When reloading the QickSoC with an external_clk=False the setting did not change because the if condition was not fulfilled. Now it checks whether the clocks have previously been set to an external_clk or not.

Hi, thank you for this excellent softare. I have a (potentially dumb) question on the signal generators - how is it possible to switch the type of generator? I am working on ZCU216 and all generators are axis_signal_gen_v4; I would like to use axis_sg_mux4_v2. Does it require recompiling the bitfile to change? Is there any documentation that would help (besides the qick docs)?

Cheers

We would like to install SLURM on the board to run Qick experiments but we are worried about having to do it as root. We know it is a Pynq limitation (see here).

Do you know if there is any recent solution to this issue?

I found that i can use Digital output I/O port by using QICK library.

But i also want to use Input function using QICK library.

I searched some QICK library detail, but i have no idea how to do that.

Do I have to use PYNQ library to use I/O input function?

thank you.

Hi i'm using zcu111 board to make DC signal and RF signal

I want to know how to change clk frequency of tProc which is now 384MHz.

Do I have to change some firmware code files? or are there any simple ways to change tProc clk frequency?

thank you

Hi folks,

I have a question about the mapping between DAC pulse_gain in the QICK configuration setting (in instructions it suggest us to try pulse_gain from 500 to 30000 DAC units). I want to know how does these numbers mapped to the AXI input number of the 14-bit DAC (0-8191)? Same question for the 12-bit ADC - how does the acquire_decimated return value mapped to the actual ADC output AXI word?

Thanks! Zhizhen

Hey folks, I'm trying to use the qick package to drive an optical setup. For part of my calibration procedure I need to be able to source raw numpy waveforms out of a DAC (no RF mixing) and measure the result on an ADC (again, no RF mixing/up or down converting).

I was hoping that this would be straightforward to do with the qick package and you folks could help me do it. Best, -Zhizhen

Hi,

I am looking into generating a variable +ve or -ve DC signal using one of the QICK signal generators. To do so, I have connected the differential outputs of DAC228_T0_CH0 P and N terminals to an operational amplifier with a split-power supply (+3.3V, -3.3V) hoping to reject the common mode and generate a +ve/-ve DC signal.

self.declare_gen(ch=0, nqz=1)
self.set_pulse_registers(ch=0, freq=0, length=1000, phase=0, gain=g, style="const") 

However, the DAC P voltage is always equal to or larger than the DAC N voltage when sweeping the gain value. I was expecting the signal generator to behave roughly like this with a bit of offset:

DAC P=DAC N, when gain=0, DAC P>DAC N, when gain>0, DAC P< DAC N when gain<0.

Is there a way to control this?

Thanks, Mutasem

In the QICK overlay and also the example here https://github.com/openquantumhardware/qick/blob/main/qick_demos/00_Send_receive_pulse.ipynb, only two ADC ports (on ADC tile 0) are activated. Is there a code or design change possible to enable more ADC ports given that there are 8 of them on the ZCU111?